IC Design Engineer

USA-CA San Jose Innovation Driveonsitemid$144K – $230K

Posted 5 days ago · via Workday

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About this role

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Key DFT Responsibilities & Skills: Tool Expertise: Extensive experience with the Siemens Tessent tool suite. DFT Architecture & Integration: Responsible for top-level DFT planning and integration. ATPG & ATE: Managing the ATPG (Automatic Test Pattern Generation) and ATE (Automated Test Equipment) interface, including ATE bring-up and failure analysis. Test Optimization: Driving test time reduction strategies.…

Read the full description on 4473 VMware, K.K.'s site →

What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

Skills match

We compare your skills against the role requirements.

Level fit

This role is mid-level. We check your trajectory against it.

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

Location fit

This role is based in USA-CA San Jose Innovation Drive. We weight your proximity and willingness to relocate.

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