SR. FPGA Design Engineer w/Active Clearance

San Diegoonsitesenior

Posted 23mo ago · via Workable

About this role

Title: FPGA Design Engineer Location: San Diego (Onsite) Term: Contract Duration: Long Term Start: ASAP Required: Active Clearance Requirements 10+ years experience FPGA Design Engineer, .Strong VHDL Skills, Deep experience with Bring-Up, Experience in Cryptography is preferred. Good experience with Packet handling and External digital interfaces Required. Experience with Microchip FPGAs a Plus Active Government Clearance Required Onsite Full-Time Required Benefits A2e Does NOT Accept Unsolicited Resumes or Referrals from any source other than the candidate, and, as a result, we will not be considering any unsolicited referrals or resumes sent to us as a fee -based candidate submittal.…

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What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

1

Skills match

We compare your skills against the role requirements.

2

Level fit

This role is senior-level. We check your trajectory against it.

3

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

4

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

5

Location fit

This role is based in San Diego. We weight your proximity and willingness to relocate.

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