Lead Software Engineer - Logic Synthesis
SHANGHAIonsitesenior
Posted yesterday · via Workday
About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: Responsible for development and maintenance of the synthesizer for Palladium. Implementation for new VHDL/Verilog feature support in synthesizer. Logic optimization and performance improvement in synthesizer. Position Requirement: This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience. Candidate should be proficient with C/C++, Operating system concepts. Design modeling using Verilog/SV, VHDL or SysC. Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: c++, claude
2
Level fit
This role is senior-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in SHANGHAI. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
c++claude