Principal DFT Engineer

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products. What You Will Do Develop and implement DFT architecture for ASIC and SoC designs. Perform scan insertion, scan chain planning, and scan compression implementation. Generate and validate ATPG patterns and analyze fault coverage results. Implement and verify MBIST, and other on-chip test features. Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration. Support JTAG and boundary-scan implementation and debug.…