ASIC Design Engineer – DSP / Analog / SerDes
San Joseonsitemid$150K – $250K
via Greenhouse
About this role
ASIC Design Engineer – DSP / Analog / SerDes
Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems.
Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.
What You Will Do
• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.…
Read the full description on Celerocommunicationsinc's site →
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, matlab, teams
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in San Jose. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonmatlabteams
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