DFT Engineer

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams. DFT Architecture & Implementation Define and implement DFT methodologies for SoCs, MCUs, or test chips. Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level. Architect innovative DFT techniques for advanced process nodes. Test Pattern Development & Validation Generate ATPG patterns for stuck-at, transition, and path delay faults.…