Physical Design Clocking Engineer

USonsitemid$106K – $149K

Posted today · via Workday

About this role

Job Details: Job Description: As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming RTL to GDS to produce design databases ready for manufacturing. On a day-to-day basis, you will execute various aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. Your work will directly contribute to optimizing design parameters such as power, frequency, and area, impacting Intel's product innovation and delivery. You will be part of the Data Center Group (DCG), a business unit focused on developing innovative solutions that power the future of computing.…

Read the full description on Intel's site →

What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

1

Skills match

For this role: split

2

Level fit

This role is mid-level. We check your trajectory against it.

3

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

4

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

5

Location fit

This role is based in US. We weight your proximity and willingness to relocate.

Score yourself on this role.
Free · no card · written explanation included
See if I'm a fit →

Skills in this role

Pulled from the job description. These are the keywords we'll weight when scoring your fit.

split

More at Intel

See all open jobs at Intel →