Senior SoC Physical Layout & Full-Chip Integration Engineer
USonsitesenior$122K – $232K
Posted today · via Workday
About this role
Job Details: Job Description: About the Role Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, teams, split
2
Level fit
This role is senior-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in US. We weight your proximity and willingness to relocate.
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Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonteamssplit
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