IC/RTL Design Engineer
mid
via Ashby
About this role
IC/RTL Design Engineer/ Front-End Engineer
About the role. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.
What you'll do
- Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
- Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, perl, teams
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in a specific location. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
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pythonperlteams