Digital Verification

Austin (Oakhillonsite

Posted today · via Workday

About this role

Job Description: Duties: Performs semiconductor design engineering duties including design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Define and write IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications). Write System Verilog (UVM) monitors, drivers, response checkers and System Verilog Assertion (SVA) cover properties to match the verification plans. Developing and maintaining portions of a verification environment including scripts and Make files. Debug failing test cases to determine source of failure and track resolution.…

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What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

1

Skills match

For this role: python

2

Level fit

We check your title trajectory against the seniority signal of the role.

3

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

4

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

5

Location fit

This role is based in Austin (Oakhill. We weight your proximity and willingness to relocate.

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Skills in this role

Pulled from the job description. These are the keywords we'll weight when scoring your fit.

python

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