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NxpLead Physical Design Engineer
Puneonsitesenior
Posted today · via Workday
About this role
We are seeking a highly skilled and experienced Synthesis & STA Engineer with ~10 years relevant experience. This role involves leading and executing RTL Synthesis & Static Timing Analysis (STA) for complex SoC designs of next-generation semiconductor products. Job Responsibilities * Lead and perform RTL Synthesis & comprehensive Static Timing Analysis (STA) at the block, sub-system, and SoC levels for cutting-edge semiconductor designs. * Develop, integrate, and maintain timing constraints (SDC) for various design hierarchies, ensuring accuracy and coverage. * Identify, debug, and resolve complex timing violations, including setup, hold, and other advanced timing checks (e.g., OCV, AOCV, EMIR, X-talk).…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: teams
2
Level fit
This role is senior-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in Pune. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
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