Physical Design Engineer- Staff to Sr. Staff
Austinonsitesenior$174K – $262K
Posted 2w ago · via Eightfold
About this role
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: QCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design Engineer to develop, optimize, and sign off advanced clocking solutions for next-generation NSP designs. The ideal candidate will have 10+ years of ASIC/SoC physical design experience , with deep expertise in high-performance clock architecture and implementation, including clock H-trees, clock mesh, and clock spine methodologies . This role requires strong understanding of the complete clock path, from clock source and distribution architecture through block-level implementation and signoff.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, perl, shell, rest, teams
2
Level fit
This role is senior-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in Austin. We weight your proximity and willingness to relocate.
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Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonperlshellrestteams
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