IC Design Verification Engineer
San Joseonsitemid
Posted 109mo ago · via Smartrecruiters
About this role
IC design verification engineer San Jose, CA Full time hire Qualifications Your primary job responsibility is to establish/enhance the verification methodology for unit-level MAC layer simulation and extend the methodology to SoC level simulation environments. In this role you will be architecting and implementing the infrastructure including test-benches, APIs, golden reference models, 802.11 specific protocol layer generators and checkers. You will also be responsible for establishing metrics and implementing tests for functional correctness, coverage, and performance characterization.…
Read the full description on Win Max Systems Corporation's site →
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, perl, teams
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in San Jose. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonperlteams
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