Digital - ASIC Design Automation & Integration Engineer
Bay Areaonsitemid
Posted 5mo ago · via Lever
About this role
Lint / CDC / Synthesis Quality · IP & Chip Integration · AI-Augmented Design Flows · CI/CD for RTL
On-Site Monday-Friday - Bay Area, CA / Vancouver, BC / Toronto, ON
Full-Time - Equity Participation - Comprehensive Benefits
ABOUT THE ROLE
Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series C funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.
We are looking for an engineer who can own the intersection of design quality, automation, and design integration.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
We compare your skills against the role requirements.
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in Bay Area. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
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