Principal Engineer

We are looking for an experienced SoC/IP Verification Engineer to lead and drive the verification of complex semiconductor designs. The role involves defining verification strategies, architecting and developing scalable constraint-random verification environments, and driving verification closure at both subsystem and SoC levels. The ideal candidate will possess strong expertise in System Verilog/UVM-based verification methodologies and hands-on experience across functional, power-aware, and gate-level verification flows. Your role Key responsibilities in your new role Lead and contribute to the definition of verification architecture and strategy for IPs, subsystems, and SoCs.…