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InfineonDES DOS SOC PDM SOI 2

Principal Engineer Design

Bangaloreonsiteprincipal

Posted 2mo ago · via Eightfold

About this role

#WeAreIn to transform theoretical concepts into real hardware designs. Are you in? Your role Key responsibilities in your new role As an engineer, Timing Closure, and Constraints Coding/Validation Engineer, you will own the architectural timing intent, constraint hygiene, and complete timing sign-off for complex, multi-million gate SoCs. You will drive multi-mode multi-corner (MMMC) timing closure from block-level implementation up to full-chip integration. A core focus of this role is using advanced optimization tools to fix critical setup, hold, transition and crosstalk violations across both functional and complex DFT modes (Scan, At-Speed, MBIST etc).…

Read the full description on Infineon's site →

What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

1

Skills match

For this role: python, r, perl, mode, teams

2

Level fit

This role is principal-level. We check your trajectory against it.

3

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

4

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

5

Location fit

This role is based in Bangalore. We weight your proximity and willingness to relocate.

Score yourself on this role.
Free · no card · written explanation included
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Skills in this role

Pulled from the job description. These are the keywords we'll weight when scoring your fit.

pythonrperlmodeteams

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