Senior Staff Engineer

We are hiring VLSI Design Engineer with expertise in Synthesis, Logic Equivalence Checks (LEC), and UPF-based Low-Power Sign-off. Experienced in low-power implementation, timing analysis, constraints development, and advanced node technologies (40nm/28nm/22nm). Proficient in Shell, Perl, and TCL scripting, with a strong track record of problem-solving, cross-functional collaboration, and driving successful design closure Your role Key responsibilities in your new role Responsible for synthesis execution, timing closure, and low-power sign-off for complex low-power SoCs targeting the IoT and MCU markets. Owned synthesis implementation and timing convergence activities at both pre-DFT and post-DFT stages for large hierarchical blocks and full-chip designs.…