Staff Engineer Design

Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation. Your Role Key responsibilities in your new role Candidate will be leading/involved in planning the modelling of analog /hard IP by means of Verilog and system Verilog. He is also expected to take part of development of modelling support pre-silicon validation. MUST have: Good understanding of modelling technique for Analog Blocks using Verilog and System Verilog. Good exposure on digital verifications, Ability to interact and work with team member in multiple geography. Good exposure to dotlib generation. Added advantage: Exposure to the MSV simulation flow.…