Staff Engineer Verification

#WeAreIn to make sure that our circuits are designed to perfection.​ Are you in? Your Role Key responsibilities in your new role create and define verification plans develop verification environments for our ICs using Universal Verification Methodology (UVM) draw on test scenarios using System Verilog verify functionality using the Constrained Random approach develop assertions in System Verilog for formal verification Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies provide proactive support to users of our verification flow environment be responsible for our verification methods Your Profile Qualifications and skills to help you succeed You have successfully completed a university degree in Electrical Engineering, C…