SoC Verification Engineer - Design for Debug/Design For Test
Indiaonsitemid
Posted today · via Workday
About this role
Job Details: Job Description: Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD) and Design for Test ( DFT ). As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling.…
What we'd score you on
reqspace match rubricFive dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.
1
Skills match
For this role: python, teams, split
2
Level fit
This role is mid-level. We check your trajectory against it.
3
Domain experience
Your work in the role's domain matters more than your years total. We weight recent and direct experience.
4
Recency
A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.
5
Location fit
This role is based in India. We weight your proximity and willingness to relocate.
Score yourself on this role.
Free · no card · written explanation included
Skills in this role
Pulled from the job description. These are the keywords we'll weight when scoring your fit.
pythonteamssplit
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