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Win Max Systems CorporationEngineering

Design Verification Engineer

Menlo Parkonsitemid

Posted 113mo ago · via Smartrecruiters

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About this role

Job Functions Develop FPGA Design Verification tests, and test plans Review Detailed Design specifications for logic to be tested Execute tests, analyze results, review RTL, determine probably source of failures, write bug reports Work with IP vendors and Design engineers to resolve bugs Desired Skills and Experience Expertise in ASIC or FPGA RTL design verification Expertise in system Verilog, and UVM Strong experience in software design, using classes Developed and used scripting languages such as TCL, Perl, and Python Experience with bug tracking (e.g. bugzilla), revision control (e.g. git), and build systems (e.g.…

Read the full description on Win Max Systems Corporation's site →

What we'd score you on

reqspace match rubric

Five dimensions, recruiter-grade. Upload your resume and we'll generate a written explanation of where you fit and where the gaps are.

1

Skills match

For this role: python, perl, git

2

Level fit

This role is mid-level. We check your trajectory against it.

3

Domain experience

Your work in the role's domain matters more than your years total. We weight recent and direct experience.

4

Recency

A skill you used last quarter weighs more than one from five years ago. We grade on recency, not lifetime.

5

Location fit

This role is based in Menlo Park. We weight your proximity and willingness to relocate.

Score yourself on this role.
Free · no card · written explanation included
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Skills in this role

Pulled from the job description. These are the keywords we'll weight when scoring your fit.

pythonperlgit

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